Presentation Abstracts
Abstracts of accepted presentations are available on IEEE Xplore.
Video Recordings and Presentations Slides
The 5th Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop featured an excellent lineup of world-renowned experts. The following video recordings* and presentation slides* of oral contributions are made freely available by the Center for E3S for educational purposes, as part of its commitment to public outreach service and broadening impact.
Opening Remarks
Eli Yablonovitch, University of California, Berkeley, USA
Director, Center for Energy Efficient Electronics Science (E3S)
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Systems Benefits of Low Operating Voltage
Paolo Gargini, IRDS, USA
Roadmap Evolution: from NTRS to ITRS, from ITRS 2.0 to IRDS
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Deep Learning and Neuromorphic Computing
Gert Cauwenberghs, University of California, San Diego, USA
Energy Efficiency of Adaptive Neural Circuits
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Masanao Yamaoka, Hitachi, Japan
An Ising Computing to Solve Combinatorial Optimization Problems
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Engin Ipek, University of Rochester, USA
Memristive Accelerators for Data Intensive Computing: from Machine Learning to High Performance Linear Algebra
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Sapan Agarwal, Sandia National Laboratories, USA
Designing an Analog Crossbar-Based Neuromorphic Accelerator
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Yichen Shen, Massachusetts Institute of Technology, USA
Deep Learning with Coherent Nanophotonic Circuits
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Novel Technologies in Computing and Communication
Jeffrey Bokor, University of California, Berkeley, USA
Prospects for Ultrafast MRAM with <10 psec Write Latency
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Lucian Prejbeanu, SPINTEC, CEA Grenoble, France
Ultrafast MRAM Strategies for Cache Applications and Beyond
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Takahiro Hanyu, Tohoku University, Japan
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing for IoT Applications
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Seth Fortuna, University of California, Berkeley, USA
Large spontaneous emission rate enhancement in a III-V antenna-LED
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Masaharu Kobayashi, University of Tokyo, Japan
Technology Breakthrough by Ferroelectric HfO2 for Ultralow Power Logic and Memory
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Recent Advances in Tunnel Switches
Ru Huang, Peking University, China
Steep Switch with Hybrid Operation Mechanism for Performance Improvement
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Jesus del Alamo, Massachusetts Institute of Technology, USA
Towards Sub-10 nm Diameter InGaAs Vertical Nanowire MOSFETs and TFETs
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Lars-Erik Wernersson, Lund University, Sweden
II-V Nanowire TFETs: Performance, Statistics, and Band Edge Sharpness
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Peter Asbeck, University of California, San Diego, USA
Modeling the Influence of Dielectric Interface Traps on I-V Characteristics of TFETs
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Sheikh Ahmed, University of Virginia, USA
Auger Effect Limited Performance in Tunnel Field Effect Transistors
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Concluding Remarks
Eli Yablonovitch, University of California, Berkeley, USA
Director, Center for Energy Efficient Electronics Science (E3S)
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*Disclaimer: The views and opinions expressed in these presentations are those of the authors and do not necessarily reflect those of the Center for E3S.